FPGA 13/13 · Stack Claude — The Answerable Question
by adrian-structure
Enforces rigorous FPGA debugging discipline to transform vague bugs into solvable root causes.
We sell high-quality skills only – not the standard knowledge any language model already has. Every skill is tested and reviewed by us before it's listed. Our goal: using our skills should let you build your own business and actually make money. Wir verkaufen ausschließlich hochwertige Skills – keine Standard-Antworten, die ohnehin jedes Sprachmodell liefert. Jeder Skill wird von uns getestet und geprüft, bevor er hier gelistet wird. Unser Anspruch: Mit unseren Skills sollst du dein eigenes Geschäft aufbauen und wirklich Geld verdienen können.
by adrian-structure
Enforces rigorous FPGA debugging discipline to transform vague bugs into solvable root causes.
by adrian-structure
Packages validated FPGA designs into deployment-ready releases for users without hardware backgrounds.
by adrian-structure
Generates auditable FPGA validation dossiers with evidence levels, error budgets, and performance metrics.
by adrian-structure
Verifies FPGA hardware behavior by comparing real-world Saleae logic captures against simulation predictions.
by adrian-structure
Automate and log FPGA bitstream programming with artifact verification and persistent flash boot checks.
by adrian-structure
Converts FPGA implementations into traceable artifacts with SHA-256 manifests and bundled implementation reports.
by adrian-structure
Automates FPGA timing closure through precise setup/hold diagnosis, CDC synchronization, and targeted pipelining.
by adrian-structure
Scripted Vivado synthesis and implementation skill with resource validation and inference tracking.
by adrian-structure
Clock-by-clock RTL simulation and verification against golden Python oracles with 4-state logic preservation.
by adrian-structure
Builds machine-verifiable, file-driven HDL testbenches with independent golden references and negative controls.
by adrian-structure
Builds provable, stateless Python reference models (oracles) for hardware verification with explicit ULP error bounds.
by adrian-structure
Generate bit-accurate Python executable specifications for FPGA hardware design and verification.
by adrian-structure
Generates synthesizable, FPGA-optimized Verilog RTL with strict hardware-ready coding standards.
by adrian-structure
Local, secrecy-grade version control for FPGA projects - every bitstream traceable to its exact source commit via SHA-256 manifest.
by adrian-structure
A 12-station proof chain for FPGA development that replaces guesswork with artifact-backed evidence.
by adrian-structure
Generates and renders validated Graphviz block diagrams and SchemDraw circuit schematics locally.
by adrian-structure
FPGA reset architecture as an area decision: why one wrong reset turns 4 BRAMs into 73,728 flip-flops, and the hybrid reset pattern that is always safe.
by adrian-structure
Radix-4 Booth multiplier design with verified RTL and an exhaustive golden model — halve your partial products without sign-extension bugs.