FPGA 05/13 · RTL Claude — Simulation vs the Oracle

The problem

Functional simulations often pass while hardware fails because "no warnings" doesn't mean "correct data." Subtle bugs like off-by-one clock shifts or silent range overflows remain invisible without cycle-accurate value comparison.

What it does

• Performs tick-for-tick value comparisons between RTL and a golden Python oracle.
• Preserves 4-state logic (X/Z) during comparison to prevent unknown states from collapsing into false zeros.
• Validates designs before and after synthesis using gate-level netlists with realistic delays.
• Injects targeted hazard vectors to catch read-after-write hazards and pipeline conflicts.
• Generates a definitive bad==0 report based on trace file analysis.

Frameworks & tools

Verilog RTL, Python oracles, Vivado, gate-level simulators, and event-driven simulation environments.

Why this beats prompting it yourself

Generic prompts ignore the nuances of event-driven simulation timing. This skill enforces strict comparison points after all nonblocking assignments, ensuring zero simulator-dependent jitter and accurate hazard detection that simple "check my code" prompts miss.

Use cases

• Verifying a new RTL block against a golden mathematical model.
• Catching synthesis-induced regressions in gate-level netlists.
• Debugging pipeline hazards and memory port conflicts with targeted vectors.
• Documenting simulation blind spots like CDC and metastability for downstream teams.

Known limitations

Cannot detect metastability, sub-cycle glitches, or clock-domain crossing issues, as these are invisible to event-driven simulators.