FPGA Proof Chain

The problem

FPGA projects often stall at "it should work" while hardware remains dead. Developers waste days debugging RTL for issues that are actually caused by timing violations, missing resets, or broken chains of custody.

What it does

• Scans project directories to identify missing proof artifacts across 12 maturity stations.
• Enforces a 60-checkpoint validation sequence from golden models to logic-analyzer measurement.
• Provides specific failure mode lessons for common issues like CDC errors and simulation mismatches.
• Generates structured handover documentation with SHA-256 bitstream tracking.
• Classifies errors between harness, RTL, and spec to prevent fixing correct hardware.

Frameworks & tools

Works with Yosys, Icarus Verilog, and major vendor toolchains (Vivado, Quartus, Libero). Scripts use Python 3.

Why this beats prompting it yourself

General LLMs often suggest Verilog fixes for hardware-level timing or reset issues they cannot see. This skill forces a rigorous physical evidence chain, ensuring you never debug a bitstream that hasn't passed timing or a testbench that lacks a golden model.

Use cases

• Auditing a legacy FPGA block to see which validation steps were skipped.
• Systematizing the sign-off process between RTL design and hardware lab testing.
• Troubleshooting "simulation-green, hardware-dead" scenarios using station-specific checks.
• Maintaining a verifiable chain of custody for bitstreams in high-reliability environments.

Known limitations

Does not write initial Verilog code, install vendor tools, or design PCBs. Requires an existing project structure with rtl/ and tb/ directories to scan artifacts.