Works with the AI Agents you already use
Claude Code
Cursor
Codex CLI
Muse
Dots+22 moreClaude CodeCursorCodex CLIMuseDots
OpenClaw
Manus
Grok
Grok Bot+18 agentsFPGA 04 Verilog Claude
Generates synthesizable, FPGA-optimized Verilog RTL with strict hardware-ready coding standards.
$10
FPGA 04 Verilog Claude
Example session with this skill installed
Write a synthesizable Verilog module for a 16-bit counter with a synchronous reset and an enable tick. Ensure it maps to the FPGA carry chain.
- Read your context and instructions
- Compiled the fpga 04 verilog
module counter_16bit (
input wire clk,
input wire rst_n,
input wire en_tick,
output reg [15:0] count
);
always @(posedge clk) begin
if (!rst_n) begin
count <= 16'd0;
end else if (en_tick) begin
count <= count + 1'b1;
end
end
endmodule
Connects securely to your tools. The creator never sees your data.
About this skill
The problem
Writing Verilog that passes simulation but fails on hardware is a common frustration. Unintended latches, blocked carry chains, and clock-domain crossing errors often stay hidden until synthesis or board deployment.
What it does
- Generates synthesizable RTL optimized for FPGA structures like LUTs, fast-carry chains, and block RAM.
- Enforces strict blocking vs. nonblocking assignment discipline to prevent simulation-synthesis mismatches.
- Implements canonical three-process FSMs with safe recovery paths and one-hot encoding options.
- Handles clock-domain crossings using two-FF synchronizers, Gray code, or handshake protocols.
- Eliminates unwanted latches by ensuring complete case/if-else coverage in combinational blocks.
Frameworks & tools
Works with Verilog-2001 and SystemVerilog (always_comb, always_ff). Optimized for FPGA synthesis tools from vendors like Xilinx (Vivado) and Intel (Quartus).
Why this beats prompting it yourself
Generic LLMs often produce simulation-only code or "spaghetti RTL" that ignores hardware constraints. This skill applies specific architectural knowledge to ensure your logic maps to physical FPGA primitives rather than generic gates.
Use cases
- Translating a verified functional spec into synthesizable RTL modules.
- Debugging "inferred latch" warnings in complex combinational logic.
- Implementing safe asynchronous FIFO pointers and clock-domain interfaces.
- Optimizing arithmetic units for fast-carry chain utilization.
Known limitations
Focuses on RTL generation; file I/O and simulation-only constructs are restricted to testbench code. Requires a clear functional specification to produce bit-accurate hardware.
How to use
Skills on Agensi run inside your AI agent. Copy the prompt, paste it into your agent, and it connects to Agensi and installs this skill for you. If a payment is needed, your agent shows it to you first.
Reviews
No reviews yet
Be one of the first to try it. Every listed skill passes our trust checks below.
Security scanned
Passed our 8-point scan before listing
Fresh listing
Recently published to Agensi
Money-back guarantee
Doesn't do what its page promises? You get your money back.
Trust & safety
Security scanned
Verified clean 1 month ago
- Passed all security checks, Safe to install