FPGA Reset Strategy

Resets are not free. This skill treats FPGA reset architecture as the area and timing decision it really is.

What you get:

• The resource-cost mechanics: a reset on a RAM blocks block-RAM inference (computed: 18,432x area per displaced BRAM — 73,728 discrete flip-flop bits for one 4096x18 buffer), a reset on a delay line blocks shift-register primitives (16x), and async styles block register packing into DSP and dedicated resources.
• The policy that follows: control-path registers get resets, datapath pipeline registers deliberately do not — with the reasoning you can defend in review.
• Correctness rules: fully-async reset hazards (recovery/removal timing, release near the clock edge), fully-sync limitations, and the standard hybrid — asynchronous assertion with synchronized deassertion — as compile-checked Verilog-2001, plus multi-clock-domain reset ordering and internally-generated-reset pitfalls.
• The synthesis interaction most guides skip: reset nets block register balancing and retiming, and the inversion workaround that unblocks them.
• A pure-stdlib reset-policy auditor: describe your registers, RAMs and delay lines as JSON, get every violation flagged with its computed cost delta and a concrete remediation.

Run python3 scripts/reset_cost_audit.py after install: five built-in cases self-test in seconds and exit 0. Every claim is backed by that runnable evidence.