FPGA 11/13 · Documentation Claude — Evidence

The problem

Engineering claims often rot into vague marketing because they lack boundary conditions. Without a traceable evidence chain, FPGA performance numbers, speedups, and accuracy claims become impossible for third parties to reproduce or verify.

What it does

• Assigns every statement an evidence level: cited source, own measurement, hypothesis, or quarantined analogy.
• Deconstructs accuracy claims into a traceable error budget chain using triangle inequality bounds.
• Generates mandatory resource usage and timing tables with used versus available metrics.
• Enforces strict separation between kernel speedup and end-to-end application speedup.
• Documents rejected optimizations and dead ends to prevent redundant future engineering effort.

Frameworks & tools

FPGA development environments, RTL simulation, gate-level netlists, hardware measurement tools (Saleae), and bitstream mapping tools.

Why this beats prompting it yourself

Writing validation dossiers manually often leads to mixing hypotheses with facts. This skill enforces a sign-off catalog of independent checks and ensures boundary conditions stay attached to every metric, preventing the "it works on my machine" fallacy in hardware documentation.

Use cases

• Creating an auditable validation dossier for FPGA IP delivery.
• Breaking down complex precision requirements into a checkable error budget.
• Documenting high-performance computing metrics with explicit counting methods.
• Performing a formal sign-off for hardware release cycles.

Known limitations

Requires raw data inputs from synthesis reports and measurement series. Does not perform the actual physical measurements or simulations.