FPGA 01/13 · Python Claude — Spec and Reference

The problem

Hardware bugs often stem from vague specifications where numerical accuracy and bit-level behavior are left to "gut feeling." Without a deterministic reference, developers resort to eyeballing waveforms, allowing silent rounding errors and initialization bugs to reach the physical FPGA.

What it does

• Generates bit-accurate Python reference models that serve as the single source of truth for hardware logic.
• Separates functional parameters from performance parameters to ensure architectural changes don't break numerical correctness.
• Derives specific word widths directly from required application accuracy to eliminate wasted logic.
• Produces intermediate state outputs for cycle-by-cycle verification against future RTL.
• Enforces strict determinism by avoiding non-deterministic loops, unset seeds, or timing-dependent logic.

Frameworks & tools

Python 3.x, FPGA Design Suites (Xilinx Vivado, Intel Quartus), Verilog/SystemVerilog, RTL Simulation tools.

Why this beats prompting it yourself

Generic LLMs often mix hardware structure with algorithmic logic, leading to non-synthesizable references or mismatched bit-widths. This skill enforces a 13-stage industrial design methodology that separates "what" is computed from "how" fast it runs, preventing common FPGA traps like uninitialized registers and heuristic termination.

Use cases

• Creating bit-accurate references for SAR bit-serial algorithms or integer square roots.
• Defining fixed-point arithmetic pipelines where rounding and overflow must be exact.
• Building testable "small instances" of large operators for exhaustive verification.
• Documenting register initial values to ensure simulation matches physical hardware behavior.

Known limitations

This skill focuses solely on the executable specification and Python reference. It does not generate Verilog code or testbenches directly, as those are handled by subsequent stations in the chain.