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Grok Bot+18 agentsSchematic & Netlist Review
Automated schematic and netlist review for hardware engineers focused on connectivity and precision analog front-ends.
$5
Schematic & Netlist Review
Example session with this skill installed
Use precision-afe-review to review examples/power-states/design.net against examples/power-states/spec.md.
Focus on the state where the controller remains powered while the receiver is off. Trace the signal path, calculate the injected current using the supplied device model, and compare it with the specified limit.
Provide a concise Markdown report with pin-level evidence, calculations, recommended next steps, and clear verification boundaries.
This is a synthetic teaching example with fictional device specifications. Do not treat its clamp model as a universal property of real devices.
- Read your context and instructions
- Compiled the schematic & netlist
Power-State Review — Off-State Injected Current
Scope & conclusion
Target: examples/power-states/design.net (Protel netlist) against examples/power-states/spec.md (synthetic fixture).
Result: the specified off-state injected current is 3.0 mA, which exceeds the 0.2 mA limit (15× the allowed value; margin −2.8 mA). The configured 1 kΩ series resistor and this clamp model
do
not meet the stated limit; normal shared-power operation is not sufficient evidence of a power-off-safe interface.
Circuit model (state S1: off state)
The relevant injection path, traced at pin level:
| Net | Members | Role |
|---|---|---|
LIVE_3V3 | J1-1, U1-1 | 3.3 V source supply |
DRIVE | U1-3, R1-1 | Controller output → series resistor |
INPUT | R1-2, U2-3 | Resistor → receiver input |
SWITCHED | U2-1 | Receiver VDD, held at 0 V by a sink (spec S1) |
RETURN | J1-2, U1-2, U2-2 | Shared return |
Trace
U1-3 (DRIVE, 3.3 V) → R1 (1000 Ω) → U2-3 (INPUT), with U2's input clamped to VDD (SWITCHED, 0 V) through an ideal clamp of 0.3 V forward drop.
Calculation
Per spec S1/S2, with driver resistance neglected and clamp drop 0.3 V:
I_inject = (V_drive − (V_VDD + V_clamp)) / R1
= (3.3 V − (0 V + 0.3 V)) / 1000 Ω
= 3.0 V / 1000 Ω
= 3.0 mA
Limit result
- Calculated injected current: 3.0 mA
- Stated limit (U2, off state): 0.2 mA
- Verdict: FAIL — limit exceeded (3.0 mA > 0.2 mA, over-limit by 2.8 mA / 15×)
Verification boundaries
Model, not device data: This is a fictional test fixture. The "ideal clamp to VDD, 0.3 V drop" is a specified model, not evidence of a real ESD/body-diode path or a guaranteed
partial-power-down (Ioff) specification.
Assumptions applied: driver output resistance neglected; VDD exactly 0 V; clamp drop 0.3 V; R1 exactly 1000 Ω. Real tolerance and temperature effects would shift the result.
No hardware operated (spec S3). No datasheet, package, or device variant was supplied, so a real-device Ioff rating remains unverified.
Not checked: reverse-direction injection, brownout/ramp states, or firmware sequencing — out of scope for this fixture.
Recommended next action (per spec S3): select a qualified power-off-isolation interface (or a controlled power sequence) using actual device specifications; this fixture does not prescribe a
universal resistor value.
Connects securely to your tools. The creator never sees your data.
About this skill
Hardware design cycles often stall due to manual, error-prone schematic reviews and netlist audits. This skill automates the inspection of circuit designs and Protel-style netlists to catch connectivity errors and precision analog front-end (AFE) misconfigurations before they hit the PCB layout phase.
What it does
- Connectivity Auditing identifies missing nets, dangling pins, and incorrect terminal mappings using Protel 2.0 netlist parsing.
- Precision Analog Review evaluates TIA stages, ADC drivers, and high-impedance paths for error budgets and biasing issues.
- Revision Comparison tracks identity mapping and netname changes between design iterations to prevent regression.
- Constraint Verification checks signal ranges, power sequencing, and isolation boundaries against component datasheets.
- Design Evidence Mapping generates traceable reports linking every finding to specific pin numbers, net names, and device specs.
How it works
- Initialize Scope: The skill identifies the target revision, power rails, and signal requirements from your design files.
- Parse Netlist: It runs local Python scripts to inventory components and trace connectivity from source to destination.
- Model Circuit: It builds a functional model of power domains, control paths, and analog signal chains.
- Execute Checks: The agent applies general and specialist hardware checklists based on the detected topology.
- Generate Report: You receive a structured Markdown report categorized by severity with explicit next steps for firmware and PCB teams.
Frameworks & tools
Uses Python 3.11 for netlist parsing and diffing. Supports Protel Netlist 2.0 dialects. Integrates with standard EDA export workflows for BOM and netlist analysis.
Why this beats prompting it yourself
Generic prompts often miss subtle pin-swaps or fail to distinguish between typical and worst-case operating limits. This skill uses structured parsing and specialized hardware references to ensure every engineering claim is backed by traceable netlist evidence rather than hallucinated connectivity.
Use cases
- Auditing a precision sensor interface for proper guarding and ADC driver stability.
- Comparing two schematic revisions to verify that a requested engineering change was implemented correctly.
- Pre-layout verification to ensure power sequencing and reset logic meet multi-rail SoC requirements.
- Identifying missing termination or protection components on high-speed interface pins.
Known limitations
Does not provide a live EDA graphical editor or visual layout routing. Netlist parsing requires Protel 2.0 headers; other dialects require custom adapters. Verify all physical pinouts manually.
How to use
Skills on Agensi run inside your AI agent. Copy the prompt, paste it into your agent, and it connects to Agensi and installs this skill for you. If a payment is needed, your agent shows it to you first.
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