fabless program review
A staged semiconductor program review toolkit for chip definition, yield modeling, and tape-out gate management.
$8
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Grok Bot+18 agentsfabless program review
Example session with this skill installed
We are at G2 for a new IoT chip. 300mm wafer, 22nm node, $5200/wafer. Die is 8.0x9.5mm. Calculate DPW and die cost with 0.15 defect density (Murphy model) and $0.45 combined package/test cost.
- Read your context and instructions
- Compiled the fabless program review
I have completed the G2 Process and Cost analysis for your IoT chip project.
Chip Economics and Yield Analysis
| Metric | Value | Notes |
|---|---|---|
| Wafer Diameter | 300 mm | Standard 12-inch wafer |
| Die Dimensions | 8.0 x 9.5 mm | Gross Area: 76.0 mm² |
| DPW (Gross) | 828 | Estimated via geometric model |
| Defect Density (D0) | 0.15 / cm² | Typical for mature 22nm node |
| Yield (Murphy) | 81.42% | Model: $Y = [(1-e^{-AD_0})/(AD_0)]^2$ |
| Net Good Die | 674 | Estimated good die per wafer |
| Wafer Cost | $5,200 | Foundry base price |
| Good Die Cost | $7.71 | Base die cost (Wafer / Net Die) |
| Fully Loaded Cost | $8.16 | Includes $0.45 Pkng/Test |
G2 Status: Conditional Go
The unit cost of $8.16 is within the initial feasibility range, but the following risks must be addressed:
- P0 Risk: 22nm capacity allocation for Q3 is not yet secured with the foundry.
- P1 Risk: IP availability for the ultra-low-power SRAM block is pending vendor confirmation.
- P2 Risk: Package substrate lead times are currently trending at 16 weeks.
Next steps
1.
Verify PDK: Confirm the actual D0 defect density with the foundry's latest quarterly report for the 22nm process.
2.
NRE Amortization: Provide expected lifetime volume to calculate the impact of mask sets and design costs on the total unit price.
3. IP Audit: Finalize the critical path IP list using references/02-process-node-pdk-ip.md.
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About this skill
Managing a chip development project requires rigorous gates to avoid multi-million dollar tape-out failures. This skill provides a structured framework for fabless semiconductor program reviews, moving from initial product definition to volume production ramp. It enforces a strict "calculate before you conclude" workflow using a built-in calculator for die-per-wafer, yield models, and NRE amortization.
What it does
- Staged gate reviews moves projects through eight defined gates from G0 (Project Kick-off) to G7 (Reliability and Ramp).
- Yield and cost modeling calculates die-per-wafer (DPW), good-die cost, and NRE amortization using standard models like Murphy or Negative Binomial.
- Tape-out readiness checks audits front-end verification, back-end physical design, DFT coverage, and ESD/clock/reset integrity.
- Infrastructure planning guides process node selection, IP sourcing, and package/test strategy development.
- Standardized reporting generates chip-spec one-pagers and tape-out gate reports with clear Go/No-Go criteria.
How it works
- Define the stage by specifying the current gate (G0 to G7) and providing current chip specs or design data.
- Execute calculations using the internal
fabless_calc.pytool to validate die area, yield targets, and unit economics. - Audit against checklists to identify P0, P1, and P2 risks across architecture, verification, and backend implementation.
- Generate deliverables using the provided Markdown templates for product definitions or sign-off reports.
Frameworks & tools
The skill utilizes a Python 3.8+ standard library calculator for semiconductor economics. It references standard industry workflows for PDK selection, MPW vs. Full Mask decisions, and OSAT (Outsourced Semiconductor Assembly and Test) planning.
Why this beats prompting it yourself
Generic AI often underestimates the complexity of chip economics and tape-out risks. This skill enforces specific industry formulas for die-per-wafer and yield modeling, ensuring that cost estimates are based on geometric reality rather than guesses.
Use cases
- Initial feasibility to determine if a target price point is achievable given a specific process node and die size.
- Tape-out sign-off to ensure all critical verification and physical design checks are closed before committing to mask costs.
- Supply chain planning to model volume ramp requirements, test time costs, and multi-sourcing strategies.
Known limitations
Calculations are estimates based on user-provided inputs. Users must verify all process parameters, IP costs, and foundry pricing with actual PDK documentation and vendor quotes.
Estimates require manual input of PDK and vendor data. Does not provide methods for bypassing IP licensing, export controls, or reverse engineering. Requires Python 3.8+ for calculation logic.
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- 1
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- 2
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- 3
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Requires
Python