Embedded & Mixed Signal Audio Hardware Design (XMOS/SHARC/+)
by blockie710
Expert guidance for high-fidelity audio PCB layout, TDM/I2S timing, and XMOS/SHARC/STM32 firmware architecture.
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You say
Calculate the BCLK for a 24-bit, 192kHz, 8-channel TDM stream and give me the series termination recommendation for the clock line.
Your agent does
BCLK = 192,000 * 32 * 8 = 49.152 MHz. Note: 32 bits per slot is standard for 24-bit TDM data alignment. Use 50 Ohm series termination resistors on BCLK and MCLK lines to prevent high-frequency ringing and EMI at these speeds.
What you get
About this skill
Design audio PCBs, firmware, and clocking that actually sound clean. Use for I2S/TDM timing, XMOS/SHARC/STM32 firmware, or USB Audio Class 2.0 endpoints.
How to install
Drop the file into your AI Agent. Works with Claude, Cursor, ChatGPT, and 20+ more.
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